embedded machine learning research engineer - georgist - urbanist - environmentalist

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Joined 1 year ago
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Cake day: June 22nd, 2023

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  • The raison d’être for RISC-V is domain-specific architecture. Currently, computational demands are growing exponentially (especially with AI), but Moore’s Law is ending, which means we can no longer meet our computational demands by scaling single-core speed on general-purpose CPUs. Instead, we are needing to create custom architectures for handling particular computational loads to eke out more performance. Things like NPUs, TPUs, etc.

    The trouble is designing and producing these domain-specific architectures is expensive af, especially given the closed-source nature of computer hardware at the moment. And all that time, effort, and money just to produce a niche chip used for a niche application? The economics don’t economic.

    But with an open ISA like RISC-V, it’s both possible and legal to do things like create an open-source chip design and put it on GitHub. In fact, several of those exist already. This significantly lowers the costs of designing domain-specific architectures, as you can now just fork an existing chip and make some domain-specific modifications/additions. A great example of this is PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability. You could clone their repo and spin up their custom RISC-V posit chip on an FPGA today if you wanted to.



  • Sounds similar to some of the research my sister has done in her PhD so far. As I understand, she had a bunch of snapshots of proteins from a cryo electron microscope, but these snapshots are 2D. She used ML to construct 3D shapes of different types of proteins. And finding the shape of a protein is important because the shape defines the function. It’s crazy stuff that would be ludicrously difficult and time-consuming to try to do manually.