Simlocks have completely vanished from the market at least here in Germany, mostly because carriers don’t care if you use your subsidised bonus phone with a different card – you’re still locked into a contract with two years or such minimum duration. Even those contracts have gotten rare though I think most people right-out own their phones and then make a separate contract.
A massive population correction is inevitable.
The world population is going to stop growing, naturally, within the next decades as the last populous countries finish their demographic transition. It’s even going to see a reduction in many places unless steered against due to way below placement rate fertility. Long story short human fertility is intimately tied to child mortality: The fewer children die, the fewer kids we have, investing in quality over quantity.
The earth can easily sustain that population, even in a more fucked up state.
For a lorry, no. For a private vehicle, yes. Standard driving licenses only allow for up to 3.5t combined permissible weight (that is, vehicle and trailer plus maximum load), 750kg of those for trailer and load. If you want to drive a combination of vehicle and trailer individually up to 3.5t (so total 7t) you need a trailer license, anything above that you need a lorry license with all bells and whistles such as regular medical checkups.
Or, differently put: A standard VW Golf can pull almost thrice as much as most drivers are allowed to pull.
A small load for a private vehicle would be a small empty caravan, or a light trailer with some bikes. A Smart Fourtwo can pull 550kg which will definitely look silly but is otherwise perfectly reasonable, that’s enough for both applications.
My kitchen scales have a USB-C port. While I certainly would like it to have the capability to stream GB/s worth of measuring data over it fact of the matter is I paid like ten bucks for it, all it knows is how to charge the CR2032 cell inside. I also don’t expect it to support displayport alt mode, it has a seven-segment display I don’t really think it’s suitable as a computer monitor.
What’s true though is that it’d be nice to have proper labelling standards for cables. It should stand to reason that the cable that came with the scales doesn’t support high performance modes, heck it doesn’t even have data lines literally the only thing it’s capable of is low-power charging, nothing wrong with that but it’d be nice to be able to tell that it can only do that at a semi-quick glance when fishing for a cable in the spaghetti bin.
A and B are the original, used for host and device sides, respectively. C is the same on both ends of the cable because figures there’s device classes which can sensibly act as both, in particular phones. It’s also the most modern of the bunch supporting higher data transfer and power delivery rates because back in the days where A and B where designed people were thinking about connecting mice and keyboards, not 8k monitors or kWhs worth of lithium batteries.
The whole mini/micro shennanigans are alternative B types and quite deeply flawed, mechanically speaking.
Forks are derivative works (quite obviously) so yes you can forbid them via license terms. Whether or not that’s still open source, take it up with OSI. I vaguely recall that at least once upon a time there was some project that required modification to the code to be published as separate patches and it was generally accepted to be open source don’t ask me which.
anyone can host an email service
Eh, no. You could in the 2000s, nowadays spam protection is so tight, and necessarily that tight, that you need at least a full-time position actively managing the server or you’re getting blacklisted for some reason or the other. Other servers will simply not accept emails sent by you if you don’t look legit and professional.
Definitely possible for a company with IT department, as a small company you want to outsource it (emails being on your domain doesn’t mean you’re managing the server), as a hobbyist, well you might be really into it but generally also no. Send protonmail or posteo or whoever a buck or something a month.
That’s the sort of thing that should just be an extension
It most likely is on the technical level, just shipped by default and integrated into standard settings instead of the add-on ones. And it’s going to be opt-in, so you won’t have to go into about:config to disable it. Speaking of: You’re looking for extensions.pocket.enabled, it should be false. And before you say “muh diskspace” it’s probably like 5k of js and css or such.
They have to be hotter than the temperature of the Sun
Well they don’t strictly speaking have to but to get fusion you need a combination of pressure and temperature and increasing temperature is way easier than increasing pressure if you don’t happen to have the gravity of the sun to help you out. Compressing things with magnetic fields isn’t exactly easy.
Efficiency in a fusion reactor would be how much of the fusion energy is captured, then how much of it you need to keep the fusion going, everything from plasma heating to cooling down the coils. Fuel costs are very small in comparison to everything else so being a bit wasteful isn’t actually that bad if it doesn’t make the reactor otherwise more expensive.
What’s much more important is to be economical: All the currently-existing reactors are research reactors, they don’t care about operating costs, what the Max Planck people are currently figuring out is exactly that kind of stuff, “do we use a cheap material for the diverters and exchange them regularly, or do we use something fancy and service the reactor less often”: That’s an economical question, one that makes the reactor cheaper to operate so the overall price per kWh is lower. They’re planning on having the first commercial prototype up and running in the early 2030s. If they can achieve per kWh fuel and operating costs lower than gas they’ve won, even though levelised costs (that is, including construction of the plant amortised over time) will definitely still need lowering. Can’t exactly buy superconducting coils off the shelf right now, least of all in those odd shapes that stellerators use.
The ISA does include sse2 though which is 128 bit, already more than the pointer width. They also doubled the number of xmm registers compared to 32-bit sse2.
Back in the days using those instructions often gained you nothing as the CPUs didn’t come with enough APUs to actually do operations on the whole vector in parallel.
graphics, video, neural-net acceleration.
All three are kinda at least half-covered by the vector instructions which absolutely and utterly kills any BLAS workload dead. 3d workloads use fancy indexing schemes for texture mapping that aren’t included, video I guess you’d want some special APU sauce for wavelets or whatever (don’t know the first thing about codecs), neural nets should run fine as they are provided you have a GPU-like memory architecture, the vector extension certainly has gather/scatter opcodes. Oh, you’d want reduced precision but that’s in the pipeline.
Especially with stuff like NNs though the microarch is going to matter a lot. Even if a say convolution kernel from one manufacturers uses instructions a chip from another manufacturer understands, it’s probably not going to perform at an optimal level.
VPUs AFAIU are usually architected like DSPs: A bunch of APUs stitched together with a VLIW insn encoder very much not intended to run code that is in any way general-purpose, because the only thing it’ll ever run is hand-written assembly, anyway. Can’t find the numbers right now but IIRC my rk3399 comes with a VPU that out-flops both the six arm cores and the Mali GPU, combined, but it’s also hopeless to use for anything that can’t be streamed linearly from and to memory.
Graphics is the by far most interesting one in my view. That is, it’s a lot general purpose stuff (for GPGPU values of “general purpose”) with only a couple of bits and pieces domain-specific.
Hooking up a BananaPi to a keyboard+monitor is going to be quite a bit cheaper, and unlike with the framework laptop you can’t re-use case, monitor, etc. with an upgraded board.
You can develop using it as an SBC, then put it into the laptop when you go to a conference to present your stuff. Or if you really want to code in the park it’s not like it’d be a microcontroller, it is fast enough to run an editor and compiler.
But granted it’s a hassle to switch out the mainboard. OTOH you can also use the x86 board as an SBC so when you’re at home it doesn’t really matter which board happens to be inside.
I guess from framework’s POV there’s not much of an argument, it’s less “do people want potato laptops” but “do we want to get our feet wet with RISC-V and the SBC market”. Nobody actually needs to use it in a laptop for the whole thing to make sense to them.
You don’t need a laptop to use a framework mainboard, they run without battery and display and everything. So if you have a Framework 13 or are in the market for one this might actually be a very nice thing, especially if the price is comparable to other boards.
ARM prominently has an instruction to deal with Javascript. And RISC-V will have those kinds of instructions, too, they’re too useful, saving a massive amount of instructions and cycles and the CPU itself doesn’t really need any logic added, the insn decoder just has to be taught a bit pattern and which microops to emit, the APUs already can do it.
What that instruction will never do in a RISC CPU though is read from memory.
On the flipside, some RISC-V macroops are CISC, fusing memory access and arithmetic. That’s an architecture detail, though, only affecting code to the degree of "if you want to do this stuff, and want it to run faster on some cores, put those instructions in this exact sequence so the core can spot and fuse them).
have variable width instructions,
compressed instruction set /= variable-width. x86 instructions are anything from one to a gazillion bytes, while RISC-V is four bytes or optionally (very commonly supported) two bytes. Much easier to handle.
vector instructions,
RISC-V is (as far as I’m aware) the first ISA since Cray to use vector instructions. Certainly the only one that actually made a splash. SIMD isn’t vector instructions, most crucially with vector insns the ISA doesn’t care about vector length on an opcode level. That’s like if you wrote MMX code back in the days and if you run the same code now on a modern CPU it’s using just as wide registers as SSE3.
But you’re right the old definitions are a bit wonky nowadays, I’d say the main differentiating factor nowadays is having a load/store architecture and disciplined instruction widths. Modern out-of-order CPUs with half a gazillion instructions of a single thread in flight at any time of course don’t really care about the load/store thing but both things simplify insn decoding to ludicrous degrees, saving die space and heat. For simpler cores it very much does matter, and “simpler core” here can also could mean barely superscalar, but with insane vector width, like one of 1024 GPU cores consisting mostly of APUs, no fancy branch prediction silicon, supporting enough hardware threads to hide latency and keep those APUs saturated. (Yes the RISC-V vector extension has opcodes for gather/scatter in case you’re wondering).
Then, last but not least: RISC-V absolutely deserves the name it has because the whole thing started out at Berkeley. RISC I and II were the originals, II is what all the other RISC architectures were inspired by, III was a Smalltalk machine, IV Lisp. Then a long time nothing, then lecturers noticed that teaching modern microarches with old or ad-hoc insn sets is not a good idea, x86 is out of the question because full of hysterical raisins, ARM is actually quite clean but ARM demands a lot, and I mean a lot of money for the right to implement their ISA in custom silicon, so they started rolling their own in 2010. Calling it RISC V was a no-brainer.
Nah phishing is a 90s term though probably coined in reference to phreaking. That started up in the 60s and by the 80s even the US had mostly switched to out of band signalling for their telephone system so none of the stuff worked any more.
You can keep the array processors fed with low IPC and frequency by having absolutely massive vector lengths, the engineering for that kind of processor isn’t in the pipeline, branch prediction etc. it’s in the APUs and how to stream data into them. Much more like GPUs, in fact RISC-V has instructions for gather/scatter.
Performance level
Not good. That bench is from a BananaPi with the same SoC, via reddit (sorry).
Maybe about an A55. If you want a performant RISC-V you’ve gotta wait until stuff leaks out of the European Supercomputer stuff onto the market though that one probably won’t have good IPC either unless it’s vector, or maybe one of the big chip design companies will grace us with a chip with a RISC-V insn decoder.
They’ve definitely done that before, dunno if it was deliberately. They must have somewhat of an idea how long it takes for nocebo to kick in with the local village idiots, if it’s short enough it could actually be a rather good idea to make waiting a bit a general policy. Tank some mild capital and opportunity cost to prevent having to battle in court and the town newspaper? Sounds like a win to me.